The inventions described and/or claimed herein generally relate to fabricating a memory device. More specifically, they relate to methods of fabricating a high-density ferroelectric memory device in which a plug is prevented from being oxidized during a high temperature heat treatment.
Efforts have been made to develop a large capacity memory device in which a ferroelectric thin film is used in a ferroelectric capacitor so that the refresh limitation of the DRAM (dynamic random access memory) can be overcome.
Such a ferroelectric random access memory (“FeRAM”) that utilizes the ferroelectric thin film is a kind of nonvolatile memory device. This FeRAM retains previously stored information even when power is not applied to the device. Its operating speed is comparable to that of DRAM. Accordingly, FeRAM is getting significant attention as a potential next generation memory device.
The charge storing material for this FeRAM device, is a ferroelectric thin film such as SrBi2Ta2O9 (“SBT”) and Pb(ZrxTi1−x)O3 (“PZT”). The ferroelectric thin film has two stable remnant polarizations (Pr). It is formed into a thin film to use it in the nonvolatile memory.
A nonvolatile memory device which uses the ferroelectric thin film, takes advantage of a hysteresis characteristic to store either a ‘1’ or a ‘0’ in accordance with a remnant polarization which is present when the electric field is removed after inputting the signals by adjusting the polarization direction in the direction of the imposed electric field.
In the FeRAM device, in the case where a ferroelectric thin film such as SrBi2 (Ta2−xNbx)2O9 (“SBTN”) or (Bi4−xLax) Ti3O12 (“BLT”) having a perovskite structure is used for the ferroelectric capacitor, there are formed upper and lower electrodes which are generally made of Pt, Ir, Ru, IrOx, RuOx, Pt-alloy or the like.
When forming the lower electrode of a capacitor by using such a conductive metal, a capacitor contact plug is first formed for a connection to the transistor which has been formed on the semiconductor substrate by forming a word line, a bit line and the like.
Then titanium silicide/titanium nitride (Ti-silicide/TiN) as a barrier metal is used, so that the adhesion between the capacitor contact plug and the lower electrode can be improved, the ion diffusion can be prevented, and the contact resistance can also be improved.
The titanium silicide/titanium nitride (Ti-silicide/TiN) layer acts to prevent the diffusion and to improve the contact resistance for the lower electrode. That is, the titanium silicide (Ti-silicide) makes the ohmic contact between the lower electrode and the plug and the titanium nitride (TiN) layer prevents the interdiffusion between the lower electrode and the plug at high temperature processes during the fabrication of the capacitor.
However, during the thermal process which is carried out at a high temperature of above 700° C. for the crystallization of the ferroelectric film, there is the problem that the ferroelectric capacitor loses its ferroelectric properties due to the oxidation of titanium silicide/titanium nitride.
Recently, in order to fabricate the FeRAM, the lowering of the crystallization heat treatment temperature is being attempted, and a plug forming process in which the plug can withstand high temperature heat treatment is being developed.
The conventional high-density FeRAM fabricating process will be described below.
FIG. 1 (PRIOR ART) illustrates the conventional FeRAM fabricating method. A dopant junction layer 13 is formed on a semiconductor substrate 11 on which a field oxide layer 12 has been formed. Then an interlayer dielectric film (ILD) 14 is formed on the semiconductor substrate 11.
Then photoresist is spread on the interlayer dielectric film 14. Patterning is carried out by exposing and developing. The patterned photoresist film is utilized as a mask to etch the interlayer dielectric film. Thus a contact hole is formed, and part of the underlying dopant junction layer 13 is exposed. Then the patterned photoresist film is removed.
Then an n-type doped polysilicon layer (“n-polysilicon”) is formed on the entire surface including the contact hole, and then, a recessing is carried out through an etch-back, thereby forming an n-polysilicon plug 15 which is buried into the contact hole.
Then Ti is deposited on the entire surface, and then, a rapid thermal nitration (RTN) is carried out at 700° C.˜900° C., so that reactions can be induced between the Ti atoms and the Si atoms of the n-polysilicon plug 15. Thus a Ti-silicide film 16 is formed on the n-polysilicon plug 15.
Under this condition, the Ti silicide film 16 forms an ohmic contact between the n-polysilicon plug 15 and the lower electrode. Then a TiN layer 17 is formed on the titanium silicide layer 16, and then, a chemical-mechanical polishing (CMP) or an etch-back is carried out until the surface of the interlayer dielectric film 14 is exposed, thereby forming a barrier metal layer. The barrier metal layer has a stacked structure of the Ti silicide/TiN layers 16 and 17. Under this condition, the TiN layer 17 serves as an interdiffusion-preventing layer between the polysilicon plug and the lower electrode.
Then a TiOx layer is formed on the interlayer dielectric film 14 including the TiN layer 17, and the TiOx layer is selectively etched to expose the TiN layer 17. Then a TiOx-adhesive layer 18 is formed on the relevant portions of the interlayer dielectric film 14.
Then, Pt and SBT are sequentially stacked on the TiO2-adhesive layer 18, and then, the Pt and SBT are selectively etched to form a stacked structure of a lower electrode 19 and a ferroelectric film 20. Then Pt is deposited on the ferroelectric film to form an upper electrode 21.
Thus in the above-described example of the conventional technique, the stacking is carried out in the sequence of n-polysilicon/Ti silicide/TiN/Pt. In this stacked structure, when a heat treatment is carried out later for the crystallization of the ferroelectric film, the Pt layer is inadequate for preventing the oxygen diffusion, and therefore, the heat treatment cannot be carried out above a temperature of 500° C.
Recently, in order to improve the oxygen diffusion prevention insufficiency at the elevated temperature heat treatment, research is being carried out to enable the use of IrO2/Ir instead of Pt.
FIG. 2 (PRIOR ART) illustrates another example of the conventional techniques. Here, IrO2/Ir is used for forming the lower electrode of the FeRAM capacitor. The process steps up to the formation of the stacked plug of TiN/Ti silicide/n-polysilicon films 17/16/15 are same as those of FIG.1 (PRIOR ART). However, the adhesive layer consists of an IrOx layer 22, while the lower electrode consists of IrOx/Ir layers 24 and 23. Further, the ferroelectric film 20 is made of SBT, while Pt is used for the upper electrode 21.
In this second example of the conventional techniques, however, the lower electrode consists of a stacked structure of IrOx/Ir layers 24 and 23, and therefore, the thickness of the lower electrode to be etched is increased. Further, when opening the iridium oxide layer 22, the titanium nitride layer 17 that lies upon the plug is liable to be damaged.
Meanwhile, in the case where SBT, PZT or the like is used for the ferroelectric film 20, the high temperature crystallization heat treatment has to be necessarily carried out, and therefore, an Ir electrode cannot be used. Even if an Ir electrode were to be used, an oxidation of Ir occurs on the interface between the SBT and the Ir electrode, with the result that the interface characteristics are aggravated. Therefore, the IrOx electrode has to be used.
Further, even in the case of a stacked structure of SBT/IrOx/TiN, an oxidation of the TiN layer occurs on the boundary between the iridium oxide layer and the TiN layer due to the presence of the iridium oxide layer.
In an attempt to solve this problem, if Ir is used under the iridium oxide layer, no oxidation occurs even at a 800° C./O2-thermal process, because Ir is excellent in preventing the infiltration of oxygen.
That is, a stacking structure is used in the sequence of n-polysilicon/Ti-silicide/TiN/Ir/IrOx).
However, if this stacking structure is used, there is formed a stacked structure of SBT/IrOx/Ir/SiO2 on the region outside the plug. That is, a weak interface is formed between the Ir/SiO2 layers, with the result that a lifting phenomenon occurs.
Accordingly, additional adhesive layer should be formed at the interface of Ir/SiO2 layers. But, in order to form the adhesive layers, an adhesive layer opening mask has to be used to open the plug region. Furthermore, the thickness of the lower electrode to be etched is increased as much as the thickness of the adhesive layer.